The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 1996

Filed:

Dec. 16, 1994
Applicant:
Inventors:

Hidemitsu Ogura, Kawasaki, JP;

Koichi Kanzaki, Kawasaki, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257315 ; 257323 ; 257435 ; 257294 ;
Abstract

A non-volatile semiconductor device comprises a memory cell having a P-type silicon substrate, an N-type diffusion region formed in the substrate and serving as a word line, N-type diffusion region one serving as a source and the other as a drain of the cell transistor, a floating gate extending from a region above the diffusion region over a region above between diffusion regions, and a bit line connected to the diffusion regions. Such a memory cell is characterized in that a passivation film is formed on an interlayer insulation film insulating the floating gate and the bit lines from each other, and that a contaminant shut-off layer is provided between the passivation film and the floating gate. With this structure, the route carrying contaminants into the cell can be shut off even during manufacture thereof, achieving a high reliability of the product.


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