The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 1996

Filed:

Dec. 28, 1994
Applicant:
Inventor:

Koichiro Okumura, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L / ;
U.S. Cl.
CPC ...
327333 ; 326 62 ; 326 81 ;
Abstract

In order to rapidly transmit a signal between circuit blocks which are located apart from each other, there is provided a driver circuit for outputting a suitable small amplitude signal and a receiver circuit receiving the small amplitude signal to restore a large amplitude signal. The driver circuit 1 is configured to output, at a node C, a signal which is in a phase opposite to that of an input signal and which changes between a power supply potential and an intermediate potential determined by an inverter circuit 102, and at a node F, a signal which is also in the phase opposite to that of the input signal and which changes between a ground potential and the intermediate potential determined by an inverter circuit 106. A receiver circuit 2 phase-inverts these signals to restore at an output terminal O a signal changing between the power supply potential and the ground potential. Since the signal amplitude is small at the lines connected between the driver circuit 1 and the receiver circuit where the wiring capacitances CL.sub.1 and CL.sub.2 are large, a signal transmission delay can be reduced.


Find Patent Forward Citations

Okumura, Koichiro. (1996). Driver/receiver circuit for reducing transmission delay (U.S. Patent No. 5543744). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5543744

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…