The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 1996
Filed:
May. 17, 1995
Richard G Cliff, Milpitas, CA (US);
Srinivas T Reddy, Santa Clara, CA (US);
Kerry Veenstra, San Jose, CA (US);
Andreas Papaliolios, Sunnyvale, CA (US);
Chiakang Sung, Milpitas, CA (US);
Richard S Terrill, Santa Clara, CA (US);
Rina Raman, Fremont, CA (US);
Robert R Bielby, Pleasonton, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgement from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.