The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 1996
Filed:
Jan. 18, 1995
Kiyoshi Nishimura, Kyoto, JP;
Hideki Hayashi, Kyoto, JP;
Jun Muramoto, Kyoto, JP;
Takaaki Fuchikami, Kyoto, JP;
Hiromi Uenoyama, Kyoto, JP;
Rohm Co., Ltd., , JP;
Abstract
Nonvolatile memory with simple structure where recorded information can be read without destroy: Voltage is impressed to control gate CG and channel is grounded at writing operation. Ferroelectric layer 32 is polarized in accordance with whether the applied voltage is larger than threshold voltage of the memory device. Control gate voltage V.sub.CC to make channel is little when the ferro-electric layer 32 is polarized with control gate side being positive (polarized with second status). Control gate voltage V.sub.CG to make channel is large when the ferroelectric layer 32 is polarized with control gate side being negative (polarized with first status). The reference voltage V.sub.ref is impressed to the control gate CG at reading operation. Large drain current flows when the ferroelectric layer is polarized with second status and little drain current flows when the ferroelectric layer is polarized with first status. Recorded information can be read by detecting the drain current. By this reading operation, polarization status is not destroyed.