Dual-port random access memory having reduced architecture

Abstract

A dual-port semiconductor memory device is disclosed that includes a number of array blocks (12) having memory cells disposed in rows and local columns, with each local column having a local bit line pair (30). A sense amplifier row (28) is associated with each array block (12) and includes a sense amplifier (28) coupled to each local bit line pair (30). Each sense amplifier row (14) is commonly connected through a number of bit line gates (32) to global bit line pairs (26) disposed on a higher fabrication layer than that of the local bit lines (30). A block decode signal commonly activates all the bit line gates (32) of one array block to couple the global bit lines (26) to one sense amplifier row (14). The global bit lines (26) are also connected to a column decoding section (18) which provides random input/output selection of a global bit line pair (26). A latch row (20) is also coupled to the global bit lines ( 26) through a number of latch gates (42). The latch gates (42) provide parallel input/output to the global bit line pairs (26). The latch row (20) is coupled to a serial shift register (22) for serial output of data stored within the latch row (20). In an alternate embodiment, there are one half the number of global bit line pairs (26) as there are local bit line pairs (30) in a given block array (12). Even and odd local bit line pairs (30) are multiplexed onto the global bit lines (26) by pairs of bit line gates (32). Correspondingly, the global bit lines (26) are multiplexed to even and odd latches (40) in the latch row (20).