The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 1996
Filed:
Dec. 20, 1994
Applicant:
Inventor:
Virinder S Grewal, Fishkill, NY (US);
Assignee:
Siemens Aktiengesellschaft, Munich, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B44C / ; C03C / ; C03C / ;
U.S. Cl.
CPC ...
216 68 ; 216 67 ; 1566431 ; 156345 ; 437228 ; 437238 ;
Abstract
A method for fabricating a stacked gate array on a semiconductor wafer. The method comprises the steps of providing a reaction chamber having an upper inductive coil and a lower capacitive electrode. The upper inductive coil is adjusted to a relatively low power setting of substantially less than 300 watts. The wafer is placed into the reaction chamber and plasma etched to provide the stacked gate array.