The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 1996
Filed:
May. 01, 1995
Robert L Canella, Meridian, ID (US);
Greg D Stevenson, Boise, ID (US);
Dave E Charlton, Boise, ID (US);
Scott A Earnest, Nampa, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
An integrated circuit testing apparatus and method of testing. In a first embodiment an amplifier amplifies the difference in a reference integrated circuit (RIC) response and a device under test integrated circuit (DUTIC) response to an electrical stimulus. The electrical stimulus is provided at an input of the DUTIC and the RIC by a stimulus circuit. A analog comparator determines when the amplified differences exceeds an adjustable threshold value. The sensitivity of the comparator is adjustable and the desired threshold value is adjusted before testing begins. If the amplified difference exceeds the threshold value of the comparator an error signal is generated. The apparatus of the invention includes a presetable counter which generates a device fail signal if a predetermined number of error signals are generated by the comparator. An initialization circuit loads a selectable value into the counter to provide a variable number of allowable errors before a DUTIC fails the test. In a second embodiment a precision voltage reference potential is adjusted to select a desired minimum potential for a high logic signal and a desired maximum potential for a low logic signal. The integrated circuit testing apparatus of the second embodiment also utilizes a RIC. The DUTIC and the RIC respond to the same electrical stimulus. The responses of the DUTIC and the RIC to the electrical stimulus are compared. If the responses have different logic levels the DUTIC automatically fails the test. If the responses have the same logic levels, the test circuit then compares the value of the DUTIC response to the minimum and maximum potentials of the precision voltage reference potential. If the DUTIC response does not lie either above or below the desired minimum and maximum potentials, respectively, the DUTIC fails the test since its potential falls within a failure window lying between the desired minimum and maximum values. Conversely if the DUTIC response falls above or below either of the desired minimum or maximum values, respectively, and has the same logic state as the RIC the DUTIC passes the test.