The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 1996
Filed:
Aug. 23, 1994
Ernest Bassous, Bronx, NY (US);
Jean-Marc Halbout, Larchmont, NY (US);
Subramanian S Iyer, Yorktown Heights, NY (US);
Rajiv V Joshi, Yorktown Heights, NY (US);
Vijay P Kesan, Ridgefield, CT (US);
Michael R Scheuermann, Katonah, NY (US);
Massimo A Ghioni, Peekskill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Silicon-VLSI-compatible photodetectors, in the form of a metal-semiconductor-metal photodetector (MSM-PD) or a lateral p-i-n photodetector (LPIN-PD), are disclosed embodying interdigitated metallic electrodes on a silicon surface. The electrodes of the MSM-PD have a moderate to high electron and hole barrier height to silicon, for forming the Schottky barriers, and are fabricated so as to be recessed in the surface semiconducting layer of silicon through the use of self-aligned metallization either by selective deposition or by selective reaction and etching, in a manner similar to the SALICIDE concept. Fabrication is begun by coating the exposed Si surface of a substrate with a transparent oxide film, such that the Si/oxide interface exhibits low surface recombination velocity. The interdigitated pattern is then etched through the oxide film by lithography to expose the Si surface and metallic electrode members are formed selectively in the exposed Si surface, using self-aligned metallization to produce thin interdigitated electrodes recessed below the silicon surface, which itself may be on a comparatively thin Si layer. The electrodes may be spaced to minimize the interdigital carrier transit time and maximize the sensitivity and the entire process and structure are compatible with conventional silicon integrated circuit (IC) technology. A further feature involves isolating the semiconductor surface layer from the substrate by a layer that may be either 1) transparent and insulating, 2) optically absorbing, or 3) optically reflecting, so that the photocarriers recombine before they can be collected by the field. In the latter case, the photodetector acts as a resonant cavity, resulting in an increase in the number of carriers that are generated, and hence a more sensitive device.