The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 1996
Filed:
Sep. 18, 1995
Youji Idei, Asaka, JP;
Hiroaki Nambu, Sagamihara, JP;
Kazuo Kanetani, Akishima, JP;
Toru Masuda, Kokubunji, JP;
Kunihiko Yamaguchi, Sayama, JP;
Kenichi Ohhata, Tachikawa, JP;
Takeshi Kusunoki, Tachikawa, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi Device Engineering Co., Ltd., Chiba, JP;
Abstract
Disclosed is a static type memory cell with high immunity from alpha ray-induced soft errors. The memory cell has a coupling capacitance C.sub.c between two data storage nodes 1 and 2. The p-well (or p-substrate) in which the driver-MOS transistors MN3, MN4 and the transfer MOS transistors MN1, MN2 are formed is connected to a V.sub.bb generator. The voltage V.sub.bb is set lower than the low level V.sub.L of the memory cell signal potential. Even when the potential variation .DELTA.V.sub.L of the low-voltage side node 2 is large, the parasitic diode present between the n-type diffusion layer corresponding to the source or drain of MN1-MN4 and the p-well (or p-substrate) does not turn on. Erroneous operations can therefore be prevented.