The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 1996

Filed:

Apr. 10, 1995
Applicant:
Inventor:

Randy C Steele, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 39 ; 326 41 ; 326 44 ; 327408 ;
Abstract

A programmable logic circuit having a routing matrix capable of providing 100% connectability and routability of a plurality of input signals to their appropriate configuration function blocks. In the present invention, input signals are first routed through the routing matrix before being processed by the input buffers. Thus, a slow user signal is processed by the relatively slow routing matrix before being provided with increased drive by the input buffers and passed on to the faster logical blocks. A number of programmable control bits are stored in SRAM. These control bits are decoded to determine which of the transmission gates of the routing matrix should be enabled. In this manner the input signal is routed to the appropriate configuration function block. Following the routing matrix is the input buffer. The highly driven output signal from the buffer is then passed to the configuration function block which performs the programmed logic functions on the signal.


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