The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 1996
Filed:
Dec. 22, 1993
Nick G Eskandari, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
The present invention provides a method and apparatus for enabling asynchronous, bi-directional communication between the CPU of a CPU-based integrated circuit and an external system having digital logic for effecting transitions between operating modes of the integrated circuit. The apparatus is utilized to inform the CPU of an interrupt request transmitted from the external system and to subsequently inform the external system of an interrupt acknowledgment transmitted from the CPU. This is accomplished by providing the CPU with a first associated register and the external system with a second associated register in addition to selector means coupled in parallel to the first register and the second register. The selector means has as a first input a first value forming an interrupt request stored in the first register and as a second input a second value forming an interrupt acknowledgment stored in the second register. The selector means further has as input a write signal from the CPU and a synchronized update signal from the external system for selecting as output from the selector means one of the first value and the second value in response to assertion of the synchronized update signal and assertion the write signal, respectively. The second register also has as input the output of the selector means for transmitting one of the first and second values to the second register which is further coupled to the first register for subsequently transmitting the selected value to the first register upon assertion of a capture signal from the external system to the first register.