The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 1996

Filed:

Aug. 17, 1995
Applicant:
Inventors:

Shuji Asai, Tokyo, JP;

Michihisa Kohno, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 40 ; 437 56 ; 437133 ; 437912 ;
Abstract

On a semi-insulative GaAs substrate, a channel layer, an electron supply layer, a threshold voltage controlling layer, an etching stop layer, a contact layer and an insulation layer are grown. By etching the insulation layer, gate openings are formed in an E-type element region and a D-type element region. With taking the gate opening as mask, dry etching is performed for the contact layer to form openings. On the inner periphery of the openings, side wall insulation layers are formed. With masking the gate opening in the D-type element region, and with taking the side wall insulation layer as mask, the etching stop layer is etched by wet etching, and threshold voltage controlling layer is etched by isotropic dry etching. After formation of the gate electrodes, source and drain electrodes are formed. By this, damaging of crystal upon formation of recess portion by etching is eliminated to prevent degradation of characteristics. Also, a source resistance can be lowered.


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