Peripheral interface having hold control logic for generating stall

Abstract

A peripheral interface unit (PIU) used by a microcontroller or microprocessor core having a pipelined architecture to access peripheral modules across a peripheral bus (PBUS). Data read or write accesses to registers in the core space are decoded and passed to the PIU. Then the access is executed across a peripheral address bus portion of the PBUS and a peripheral data bus of the PBUS by the PIU. In a pipelined architecture, during any one cycle there could exist up to two read accesses and one write access to the core registers. The PIU provides the needed logic to arbitrate these three access across the PBUS. In such cases the PIU inserts proper pipeline stalls until all the accesses are completed. All read accesses from the core registers cause at least a one state pipeline stall. Write accesses only stall the pipeline if two core register writes follow each other and the PBUS is not ready at the time of the second access or if a read and write occur at the same time. The PIU prioritizes and arbitrates these accesses. During any one cycle, write operations have the highest priority, followed by read operations on a first source bus and then read operations on a second source bus. The write operation is first since the write is from the previous instruction, and the reads are from the current instruction. The order of the read instructions is chosen to ensure that the least critical read is performed last.