System for generating snoop addresses and conditionally generating

Abstract

A processor and a memory address bus, a processor and a memory data bus, and a data transfer control unit are provided to a multiprocessor computer system comprising a first and a second processor, a first and a second corresponding private cache, a pipelined memory shared among the processors, an I/O device, and a cache coherency mechanism for maintaining cache coherency. I/O data stored in the shared memory are cacheable in the private caches. The processor and memory address and data buses are advantageously used to couple these elements and to control data transfers in and out of the shared memory. All data transfers in and out of the shared memory are made in multiples of the basis on which cache coherency is maintained, and through the data transfer control unit. As a result, minimum complimentary cache coherency actions, in addition to those provided by the cache coherency mechanism, are required of the data transfer control unit and the caches, to allow data to be transferred between the shared memory and the I/O device. Furthermore, successive cache coherency basis transfers between the shared memory and the I/O device are overlapped, thereby improving the overall performance of the multiprocessor computer system.