The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 1996

Filed:

Feb. 06, 1995
Applicant:
Inventors:

Tetsuya Ueda, Kikuchi, JP;

Kazunari Michii, Kikuchi, JP;

Yutaka Koyama, Kikuchi, JP;

Naoto Ueda, Kikuchi, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437211 ; 437209 ; 437214 ; 437217 ; 437220 ;
Abstract

In a method of manufacturing a semiconductor device, overlaid on a first lead frame including a die pad supported by a plurality of die pad suspending leads is a second lead frame having connecting leads wherein the first and second lead frames are disposed on a first molding die such that the die pad and inner lead portions of the inner leads of the second lead frame are accommodated within a first cavity of the first molding die while offset portions of the die pad suspending leads are disposed outside of the first cavity. A second molding die is clamped onto the first molding die to define a resin molding chamber which is then filled with a molten resin to form a package. After removing the package from the first and second molding dies, the offset portions are cut away from the package while cutting the connecting leads to a predetermined length. A semiconductor chip as large as permissible can be embedded within a semiconductor device of a standard size while ensuring high quality and improved reliability of the semiconductor device.


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