The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 1996
Filed:
Apr. 27, 1996
Jau-Jey Wang, Hsin-Chu, TW;
Ming-Hsung Chang, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Hsin-chu, TW;
Abstract
A salicide process for manufacturing a lightly doped drain (LDD) MOS transistor having unshorted titanium silicide gate electrode and source/drain contacts. The salicide method comprises forming a titanium (Ti) layer on the surface of the substrate, the sidewall spacers and the gate electrode. Nitrogen is implanted at a large angle into the Ti layer, especially over the sidewall spacers, thus converting all the titanium layer over the spacers to titanium nitride. Next, the titanium layer is thermally annealed forming titanium silicide on the top surface of the gate electrode and in the highly doped source/drain regions. The titanium nitride layer and any of the remaining titanium layer is etched away thereby leaving unshorted titanium silicide on the top surface of the gate electrode and in the highly doped source/drain regions. The TiN layer over the sidewall spacers prevents a titanium silicide bridge from forming between/he gate electrode and the source/drain regions during the thermal anneal process. This prevent electrical shorting between titanium silicide on the top surface of the gate electrode and the highly doped source/drain regions.