Apparatus and method for minimizing verify time in a semiconductor

Abstract

An apparatus and method are described for minimizing the time required to perform verify operations in a semiconductor memory having a memory cell capable of being programmed, erased, and repaired, such as a flash EEPROM (electrically erasable programmable read only memory). The apparatus minimizes the time required to verify that the memory cell was correctly programmed, erased, and repaired. The apparatus includes a word a decoder, a driver, and a means for switching voltage levels supplied to the decorder and driver. The driver is comprised of a p-channel transistor having an n-well electrically coupled to a first power line, and a p-substrate. When the memory cell is to be accessed, the driver is activated and drives the word line with a voltage on a second power line. The the second power line is switched from a first voltage level to a second voltage level in order to initiate a verify process while the first power line is maintained at an approximately constant voltage. Any inherent diffusion junction capacitance between the n-well and the p-substrate is kept substantially at a constant charge. By coupling the driver n-well capacitive load to the first power line, there is no need to wait for the driver n-well capacitance to discharge between program and program verify operations. Thereby, the amount of time required to perform a program verify is minimized.