The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 1996

Filed:

Jul. 22, 1994
Applicant:
Inventors:

Atsuo Watanabe, Hitachiota, JP;

Kazushige Sato, Hitachi, JP;

Takahiro Nagano, Hitachi, JP;

Shoji Shukuri, Koganei, JP;

Takashi Nishida, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 31 ; 437 59 ; 437 74 ; 437 75 ; 437153 ; 148D / ; 257370 ; 257378 ;
Abstract

A semiconductor device includes a plurality of semiconductor regions of a first conductive type and a plurality of semiconductor regions of a second conductive type. AMOS transistor having a channel of the second conductive type is formed in the semiconductor regions of the first conductive type, and a bipolar transistor and a MOS transistor having a channel of the first conductive type are formed in the semiconductor regions of the second conductive type. Each of the semiconductor regions of the first conductive type is made up of a semiconductor layer where the impurity concentration decreases with the depth from the surface thereof, a first buried layer of the first conductive type which is formed in a semiconductor substrate and where the impurity concentration distribution in the direction of thickness has a single peak value, and a second buried layer of the first conductive type which is formed between the semiconductor layer and the first buried layer and where the impurity concentration distribution in the direction of thickness has a single peak value. The first and second buried layers are formed by the ion implantation method, after an epitaxial growth process and a field oxidation process have been completed.


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Watanabe, Atsuo. (1996). Method of fabricating bipolar transistor having high speed and mos (U.S. Patent No. 5506156). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5506156

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