The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 1996

Filed:

Sep. 30, 1993
Applicant:
Inventors:

Kee S Kim, Folsom, CA (US);

Leonard J Schultz, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
371 223 ; 324 731 ;
Abstract

A scan chain for testing sequential logic circuitry includes a number of concatenated storage elements having a feedback loop from the output of the last storage element to the input of the first storage element. The storage elements are clocked by a chain clock signal at a frequency multiple of a base frequency. The number of storage elements in the scan chain is a relative prime with respect to the frequency multiple. Scan chains running at different frequency multiples of the base frequency may be concatenated with the output of the last storage element of one scan chain being coupled to the input of the first storage element of the next scan chain. Wherever the output of a storage element clocked on a leading phase of the chain clock signal is coupled to the input of a storage element clocked on a trailing phase of the chain clock signal, a buffer is inserted to buffer the output to the input.


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