Low voltage fowler-nordheim flash eeprom memory array utilizing single

Abstract

A memory array (10) is provided with a plurality of Flash EEPROM memory cells (24) that are fabricated with a single level poly process. Each of the transistor cells (24) is fabricated from a single poly layer floating gate (40) that extends between a moat region (30) and an implanted region (80), comprising the control gate of the cell (24). The portion of the floating gate (40) overlying the moat forms a channel region and is separated therefrom by a thin tunnel oxide layer (82) to allow the cell to operate in accordance with Fowler-Nordheim tunneling. The portion of the floating gate (40) disposed over the implanted control gate (80) is separated therefrom by a layer of oxide (84). The implant region (80) is contacted by a contact layer (86) to allow voltage to be applied thereto. The transistor is contained within a P-tank (78) which is disposed at a negative voltage, this tank (78) contained within an N-tank (76), which tank ( 76) is disposed at a higher voltage. This assures that no conduction occurs from the region (80) to the tank (78) when negative voltages are applied to the control gate. Negative medium voltages and positive medium voltages are utilized to allow the array to be bit programmed without using separate row select transistors.