The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 1996
Filed:
Jul. 29, 1993
Applicant:
Inventor:
Seiichi Iwamatsu, Suwa, JP;
Assignee:
Seiko Epson Corporation, , JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437187 ; 437 50 ; 437195 ; 437194 ;
Abstract
A method for forming optimized film metal interconnects employed in integrated circuit structures have a width, L, and a spatial separation or spacing, S, according to the following characteristics: interconnect width, L.gtoreq.0.1 mm; interconnect spatial separation, S.gtoreq.0.2 .mu.m, interconnect thickness, T.sub.A1 .ltoreq.2L mm; and interlayer insulating film thickness, T.sub.I .ltoreq.2L min. More particularly, the layout is characterized by having the ranges of 0.1.ltoreq.L.ltoreq.0.8 mm and 0.2 mm.ltoreq.S.ltoreq.1 mm. As a result, IC signal switching speed is optimized for IC's designed in the sub-micron integration scale regime.