The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 1996
Filed:
May. 12, 1994
Noriaki Sato, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
An erasable-programmable read only memory (EPROM) allowing a miniaturization of an isolation region (a field insulating layer) without generating a parasitic transistor. The EPROM includes a semiconductor substrate, a field insulating layer defining a device formation region of the semiconductor substrate, a gate insulating layer and a floating gate formed on the field insulating layer and the field insulating layer. The EPROM further includes a trench insulating layer extending into the semiconductor substrate at the center portion of the field insulating layer so that one of the side walls of the trench insulating layer is self-aligned with the end face of the floating gate. A first interlaminar insulating layer covers the floating gate, and a control gate is located above the first interlaminar insulating layer. A second interlaminar insulating layer is formed over the control gate and a bit line is formed on the second interlaminar insulating layer.