The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 1996
Filed:
Sep. 22, 1994
Donald C Mayer, Palos Verdes, CA (US);
Kenneth P MacWilliams, Redondo Beach, CA (US);
The Aerospace Corporation, El Segundo, CA (US);
Abstract
A gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET) includes a source, channel and drain surrounded by a top gate and a buried bottom gate, the latter of which also has application for other buried structures and is formed on a bottom gate dielectric which was formed on source, channel and drain semiconductor layer. After forming a planar bottom insulator layer on the bottom gate and bottom gate dielectric, the device is flip-bonded to an oxide layer of a bulk silicon wafer, thereby encapsulating the buried bottom gate electrode in insulating oxide. The semiconductor layer forms the source, drain and channel in a mesa structure on which is deposed a top gate dielectric, a top gate, and top gate insulator as well as four conductors for connecting to the source, drain, top gate and bottom gate. The latter two electrodes can be independently controlled or commonly controlled for enhanced operation of GAA MOSFET having improved isolation and reduced parasitic capacitance due to the use of encapsulating insulation layers of the merged wafer consisting of two bonded wafers.