The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 05, 1996
Filed:
Jan. 26, 1995
Fernando Gonzales, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
This invention is a DRAM array having stacked-capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a 5-mask process for fabricating such an array. The array has a cross-point cell layout (i.e., a memory cell is located at each intersection of each digit line and each word line) and tungsten digit lines formed using a damascene process buried in the substrate. Each cell in the array has a vertical transistor, with the source/drain regions and channel region of the transistor being formed from epitaxially grown single crystal silicon. The stacked capacitor is fabricated on top of the vertical transistor.