The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 1996

Filed:

May. 19, 1994
Applicant:
Inventors:

John E Cronin, Milton, VT (US);

Carter W Kaanta, Colchester, VT (US);

Randy W Mann, Jericho, VT (US);

Darrell Meulemans, Jericho, VT (US);

Gordon S Starkey, Essex Junction, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437187 ; 437235 ; 437236 ; 437195 ; 437 40 ;
Abstract

Fabrication methods and resultant semiconductor structures wherein stack structures are selectively insulated from an enveloping layer of local interconnect material. The fabrication methods involve forming an overpass insulator(s) simultaneously with the underlying gate. Specifically, a layer of non-erodible insulating material is deposited over a layer of conductive material roughly in the area to comprise the stack structure. A simultaneous etch is then performed, and the resultant insulator portion is self-aligned to the underlying conductive material. The insulator portion insulates the stack from a subsequently deposited and planarized layer of local interconnect. Further processing options include decoupling silicide formation on selected stack structures, and various planarization and etching approaches for different available technologies. Specific details of the fabrication methods and resultant structures are set forth.


Find Patent Forward Citations

Loading…