High-speed low-power cmos pecl i/o transmitter

Abstract

An output buffer contains a totem-pole structure of four CMOS transistors. The top two are PMOS devices and the bottom two are NMOS devices. The top and bottom transistors function as output current switches which alternatively turn on and off the current flow from either VSS or VDD to the resistive termination load Rt. The middle two devices are connected to DC voltage references which control a precise amounts of current sourced to a load using a precision current source and sunk from a load using and to a precision current sink. The reference voltages for the precision current source and the current sink uses a negative feedback circuit which is referenced to a resistor ladder and a current source controlled by a band-gap reference source. This allows for on-chip referencing of ECL levels and control of reference voltages and currents in spite of variation is process, voltage, and temperature. Internal ECL reference levels signals V.sub.OL and V.sub.OH are used to control the output levels. Operational amplifiers drive the respective transistors such that voltage at the drains of the current source and sink transistors equals the ECL reference inputs VOH and VOL. These control voltages generate a precise currents through a replica stage and are also applied to the output stage. All of the devices in the reference control circuit are scaled to reduce DC power dissipation. For differential operation, a second totem-pole driver circuit is used with the inverse input data signal for controlling the output current switches.