The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 1996

Filed:

Sep. 14, 1993
Applicant:
Inventors:

Kazuhiro Sakashita, Itami, JP;

Isao Takimoto, Itami, JP;

Terukazu Yusa, Itami, JP;

Takeshi Hashizume, Itami, JP;

Tatsunori Komoike, Itami, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C06F / ;
U.S. Cl.
CPC ...
364489 ; 364490 ; 364491 ; 364488 ;
Abstract

A register circuit an arithmetic circuit a register circuit and a logic circuit form a bit slice cell corresponding to a path of propagation connecting the circuits in this order. Similarly, an arithmetic circuit register circuits and a logic circuit form a bit slice cell and an arithmetic circuit register circuits and a logic circuit form a bit slice cell. The bit slice cells are arranged generally in parallel to form a bit slice circuit which prevents redundant lines for connecting the functional circuits, whereby the bit slice circuit is developed in a short period without a decreased degree of integration and prolonged delay time.


Find Patent Forward Citations

Sakashita, Kazuhiro. (1996). Integrated circuit device and method of designing same (U.S. Patent No. 5493506). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5493506

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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