The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 1996

Filed:

Feb. 17, 1994
Applicant:
Inventors:

Ken-ichiro Matsuzaki, Yokohama, JP;

Shigeru Nakajima, Yokohama, JP;

Nobuhiro Kuwata, Yokohama, JP;

Kenji Otobe, Yokohama, JP;

Nobuo Shiga, Yokohama, JP;

Ken-ichi Yoshida, Yokohama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257287 ; 257194 ; 257285 ; 257401 ; 257657 ;
Abstract

This invention provides a high-speed FET with a sufficiently high output current, and an FET having a high mobility of channel electrons and a high electron saturation rate. For this purpose, in this invention, a buffer layer, a first channel layer, a first spacer layer, a second channel layer, a second spacer layer, a third channel layer, and a capping layer are sequentially epitaxially grown on a semi-insulating GaAs semiconductor substrate. Drain and source regions are formed, and a gate electrode is formed to Schottky-contact the capping layer. Drain and source electrodes are formed to ohmic-contact the drain and source regions. Extension of a surface depletion layer from the substrate surface to a deep portion is prevented by the third channel layer closest to the substrate surface. For this reason, a sufficient quantity of electrons for forming a current channel are assured by the second and first channel layers.


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