Late cancel method and apparatus for a high performance microprocessor

Abstract

A late cancel method and apparatus for a high performance microprocessor system is disclosed. The invention is advantageously utilized in a microprocessor system comprising a processor, an external cache memory and a main memory. The processor incorporates logic to determine whether an access directed to the external cache memory has resulted in a cache hit or miss. In operation, the processor requests a desired instruction from the external cache memory which provides a cache word and cache tag to the processor before a validity determination has been made. The processor determines whether the instruction is valid, while concurrently, the processor begins to pre-decode and decode the cache word as an instruction. If the processor determines that a cache hit has occurred, the cache word proceeds normally through decoding to execution by the processor. Alternatively, if the processor determines that a cache miss has occurred, the cache word is canceled such that the results of any pre-decoding or decoding are eliminated from the processor pipeline, and the instruction is not executed. The processor further halts the processor pipeline and obtains the desired instruction from main memory.