The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 1996
Filed:
Apr. 15, 1994
Gordon P Pollack, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method for forming a mesa-isolated SOI transistor using a split-process polysilicon gate including the steps of depositing a layer of buried oxide (14) on a silicon substrate (12), depositing an SOI layer (16) on buried oxide layer (14), and forming a gate oxide layer (18) on the SOI layer (16). Further steps are to form a gate polysilicon mesa (20) on the gate oxide layer, and an SOI mesa (28) on gate polysilicon mesa (20) and forming an oxide sidewall (26) on the gate polysilicon mesa (20) and SOI mesa (28). A gate electrode (38) is the formed along with an oxide sidewall (36). Implanting gate electrode (38) with a boron implant occurs next, after which an oxide sidewall is formed on the gate electrode (38). The gate electrode (38) is implanted with phosphorus to form source and drain region. Thereafter annealing the structure takes place.