The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 1996
Filed:
Aug. 03, 1993
Muthurajan Jayakumar, Folson, CA (US);
Ronald Mosgrove, Portland, OR (US);
Hugh Bynum, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A process for generating an interrupt of programmable priority for a piece of embedded hardware associated with a first interrupt controller providing interrupts for a processor having a priority which is not programmable in a computer system including a second interrupt controller providing interrupts for the processor having a priority which is programmable. The process for causing the interrupts furnished by the first controller for the embedded hardware device to have programmable priority including the steps of generating a general interrupt at the output of the first interrupt controller in response to a signal to the first processor from the associated embedded hardware device, transferring the general interrupt to the second interrupt controller, responding to the general interrupt by signaling the associated processor that a general interrupt has been received by the second interrupt controller from the first interrupt controller, determining from the first interrupt controller the particular embedded hardware device which caused the generation of the general interrupt, and selecting an interrupt handier routine from memory for the particular embedded hardware device to provide an interrupt vector for the particular embedded hardware device to the second interrupt controller.