Concurrent cache line replacement method and apparatus in microprocessor

Abstract

A concurrent cache line replacement method and apparatus for a high performance microprocessor system with a write-back cache memory is disclosed. The invention is advantageously utilized in a microprocessor system comprising a CPU, a write back cache memory, DRAM main memory, a cache and DRAM controller (CDC), and a data path unit (DPU) with a write buffer capability. In accordance with the method of operation of the present invention, when a read access by the CPU results in a cache miss to a dirty cache line, the CDC concurrently initiates two operations. The CDC initiates the writing of the dirty line in the cache memory to a write buffer in the DPU, while concurrently, the CDC also initiates the reading of the new line from the DRAM main memory. With respect to the writing of the old line from cache memory to the write buffer in the DPU, at some time subsequent to the initiation of this operation, the CDC completes the writing of the old line to the DPU and internally notes this completion, and at a later point in time, the CDC is able to transfer of the old line from the write buffer in DPU to the DRAM. With respect to the reading of the new line from the DRAM main memory, initiated concurrently with the preceding write operation, this read operation overlaps in time with the single restriction that the CDC not cause the new line to actually be written to the cache memory until the writing of the old line to the write buffer in the DPU is completed. Alternatively, the restriction can be tailored to apply at the d-word level.