Single ram multiple-delay variable delay circuit

Abstract

A multiple-delay variable delay circuit uses a random access memory (RAM) array to provide adjustable delay of a block of input data, such as previously necessitated use of an extensive shift register configuration. A single RAM array, having a given capacity, is used to economically provide individual delays to a plurality of blocks of input data, with the aggregate of the individual delays not exceeding the capacity of the single RAM array. Time-shared use of a high speed RAM enables simultaneous single-port processing of data blocks, with delay control circuits providing utilization of separate portions of the RAM capacity, to provide individual delays resulting from successive read/write cycles utilizing a desired total of incremental delays. Simplified delay control circuits provide manufacturing and operating economies with single-port or multi-port RAM arrays.