High-stability cmos multi-port register file memory cell with column

Abstract

A memory cell has the read current from the bit lines isolated from the bistable storage latch in the cell. Internal nodes of the bistable storage latch control isolated gates of MOS read transistors which gate the read current from the bit lines to a local node within the memory cell. The read current is then switched to ground from the local node by a read switch transistor. The read switch transistor is gated by the read row line. The read current is isolated from the read row line because the read row line is only connected to the isolated gate of the read switch transistor. The read current is also isolated from the bistable storage latch since the read transistors are connected at their isolated MOS gates to the bistable's nodes. This isolation of the read current allows additional read ports to be added without disrupting the cell's stability or write performance. The read ports are optimized independently of the bistable stability and write performance and even optimized independently of other read ports. For allowing better control of the read currents, a current-mirroring row driver causes the current in the row driver to be mirrored by the read currents flowing through the read switch transistors.