Fifo buffer with full/empty detection by comparing respective registers

Abstract

A method and apparatus for generating control signals for a high speed First In First Out (FIFO) buffer. Moreover, the present invention limits the instances where signal glitches may occur. A first pair of circular shift registers are used to control writing data to and reading data from the FIFO. The outputs of each register in each shift register are coupled to enable individual read and write lines of a FIFO memory device. A single logical one value circulates through the shift registers to indicate a FIFO location where data may be written to or from. Toggle latches are coupled to each shift register. The values in the toggle registers change responsive to a read or write operation. By comparing the logical one values in the corresponding positions in the shift registers, and considering the values from the toggle latches, EMPTY and FULL conditions are detected. Further, ALMOST EMPTY and ALMOST FULL signals are generated through a second pair of circular shift registers which shadow the operation of the first pair of circular shift registers. The second pair of circular shift registers is preset with one or more logical one values. By comparing the logical one values in the corresponding positions of the first and second pairs of shift registers, the ALMOST EMPTY and ALMOST FULL conditions are detected.