The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 1995

Filed:

Jul. 20, 1993
Applicant:
Inventor:

Daniel Seligson, Palo Alto, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395 27 ; 395 22 ; 395 23 ; 395 24 ; 395 11 ;
Abstract

An integrated circuit lattice chip for computation of dynamic programming (DP) recursions uses identical nodal processor units arranged in regular lattice form. Interconnections between processor units on the chip are programmable using non-volatile EEPROM connections. The nodal processor units have computing element for generating a distance metric representative of the difference between the i.sup.th and j.sup.th elements of the unknown and prototype vectors that is combined with a maximum partial or minimum cumulative distance metric of preselected set of lower order nodal processors to produce an optimal (maximum or minimum) cumulative distance value for unknown and prototype vector elements with indices equal to or less than (i, j). A network is also provided for identifying the optimal path through the lattice for use in designing a DP classification system.


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