Fractional speed bus coupling

Abstract

Apparatus for enabling internal data processing logic including a number of units clocked at a first frequency to operate with an external bus operating at a second frequency that is a fraction m/n of said first frequency. A first bus is connected via readers to data latched for data transfer from the number internal units of the data processing logic to the data latches. A second bus is connected via drivers to the data latches for data transfer from internal bus units to the data latches. The data latches are connected to the external bus. A control circuit connected to the readers and drivers controls the readers and drivers to guarantee that sampling is done when logic is stable. The control circuit includes priority logic for determining priority between the units for permitting a high priority unit to transfer data on the external bus. Upon the condition that m=1 and n is any positive integer, transfer of data from the external bus to the first bus occurs at the point in time that the internal clock and the external clock are aligned. Upon the condition that m=2 and n is any positive odd integer, transfer of data from the external bus to the second bus occurs at the point in time that the internal clock and the external clock are aligned. The priority logic prevents enabling the drivers during any period during which the internal clock and the external clock are not aligned.