Setup or hold violation triggering

Abstract

One embodiment of a circuit and corresponding method for generating a trigger signal upon the occurrence of either set up or hold time violations in the same waveform acquisition produces a trigger signal referenced to, but displaced in time from, the input clock signal. Transitions (13) in a data signal initiate a window pulse (14') whose duration is equal to the sum of a set up time requirement and a hold time requirement. The window pulse is used as the D input to a flip-flop (20) that is clocked by a version of a clock signal whose active edge has been delayed (28) for an interval that corresponds to the hold time requirement. The output of the flip-flop (20) is a trigger signal that only occurs when a set up or hold time violation has occurred. In another embodiment, triggers generated as the result of a set up time violation are referenced to the clock edge, while triggers that are generated as the result of a hold time violation are referenced to a transition in the data signal. Data transitions (40) initiate a pulse (46 ) whose duration is the set up time. This pulse is the D input to a first flip-flop clocked by the clock signal. A second flip-flop (54) is clocked by data transitions and receives at its D input a pulse (48) that is initiated by an active edge of the clock signal and whose duration is the specified hold time. The outputs of the first and second flip-flops are ORed (56) to produce the trigger.