The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 1995
Filed:
Jun. 24, 1994
Applicant:
Inventors:
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518501 ; 257315 ; 257316 ; 257389 ; 257396 ;
Abstract
A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.