Memory array utilizing low voltage fowler-nordheim flash eeprom cell

Abstract

A Flash EEPROM memory array includes a plurality of transistor memory cells (24) arranged in rows and columns. The sources of the transistors (24) are connected to Virtual Ground Lines (29) and the drains thereof are connected to Column Lines (28). The memory cells (24) are programmable by Fowler-Nordheim tunneling. Each cell also includes an isolation structure having a first isolation tank of the first conductivity type material for surrounding each of the floating gate transistor memory devices and a second isolation tank of a second conductivity type material opposite to the first conductivity type surrounding the first isolation tank, allowing application of a negative voltage to the source or drain of the cell. Initially, all of the transistors are erased in the FLASH ERASE operation by disposing the Word Lines at a negative medium voltage and the Bit Lines at a positive medium voltage. Thereafter, selected transistors can be written to by selectively charging the floating gates in the transistors. This is achieved by disposing the Column Lines (28) of a select transistor at a negative voltage of a magnitude less than the programming voltage V.sub. PP and disposing the row line (26) of the select transistor at a positive voltage of a magnitude less than V.sub.PP.