Logical operation method employing parallel arithmetic unit

Abstract

A logical operation method for evaluating a train of output data to be obtained when a plurality of input patterns are successively applied to a memory element whose output value depends upon a sequence of input values. For each of the plurality of patterns in time series, the method decides whether or not the pertinent pattern is a holding pattern which means that the output value of the memory element depends upon a preceding pattern. Subsequently, the method evaluates a first train of data which consists of flags each indicating whether or not the respective pattern is the holding pattern, and a second train of data which consist of a predetermined logical values for the holding patterns and output logical values of the memory element for the non-holding patterns. Finally, the method subjects the first and second trains of data to operations in parallel by the use of a parallel arithmetic unit, thereby obtaining the train of output data of the memory element in parallel. High-speed logic/fault simulations can be realized even for a synchronous sequential circuit with the parallel arithmetic unit such as vector computer. This makes it possible to sharply reduce the number of man-hour and shorten the processing period of time in the verification of logic and the generation of test data.