The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 1995
Filed:
Feb. 15, 1994
Applicant:
Inventors:
Gordon W Motley, Ft. Collins, CO (US);
Peter J Meier, Ft. Collins, CO (US);
Brian C Miller, Ft. Collins, CO (US);
Assignee:
Hewlett-Packard Company, Palo Alto, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
327185 ; 327199 ; 327208 ; 327202 ;
Abstract
A CMOS latch circuit having a second feedback inverter and a switching circuit to switch the second feedback inverter out of the circuit when the latch is being loaded. A first circuit implementation uses a single PFET as the switching circuit, and a second circuit implementation incorporates an NFET transistor, in parallel with the PFET. In a third circuit implementation, the switching circuit switches power to and from the second feedback inverter rather than switching the output signal of the inverter to reduce the input capacitance of the latch.