The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 1995
Filed:
Jun. 06, 1994
Tzu-Yin Chiu, Martinsville, NJ (US);
Frank M Erceg, Bethlehem, PA (US);
Francis A Krafty, Bangor, PA (US);
Te-Yin M Liu, Hsin-Chu, TW;
William A Possanza, Northampton, PA (US);
Janmye Sung, Warren, NJ (US);
AT&T IPM Corp., Coral Gables, FL (US);
Abstract
A process for fabricating transistors on a substrate is disclosed. In accordance with the process, stacks of material are formed on the surface of the substrate. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. A first layer of polycrystalline material is deposited over the substrate and selectively removed such that only those portions of the polycrystalline layer that surround the stacks of material remain. A layer of silicon nitride or silicon dioxide is then formed over the substrate surface. A first resist is then spun on the substrate surface. This resist aggregates near the stacks of material. An isolation mask is generated that leaves exposed only those areas of the substrate that correspond to the area of overlap between the first polycrystalline area and the stacks of material, which also contain a layer of polycrystalline material. The substrate is then subjected to an etchback process to remove the portion of the polysilicon material that overlaps the material in the stacks.