The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 1995

Filed:

Jan. 04, 1994
Applicant:
Inventors:

Richard W Gurtler, Mesa, AZ (US);

Henry G Hughes, Scottsdale, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
29895 ; 29830 ; 1566301 ; 1566331 ; 437192 ;
Abstract

A method electrically and mechanically interconnects two surfaces of high density first and second semiconductor devices. The first semiconductor device (10) is formed with plug members (22) connected to nodes (18) of its circuit elements (14) and protruding from the first semiconductor device. The second semiconductor device (24) is formed having receptacle members (36) connected to nodes (32) of its circuit elements (28) and protruding from the second semiconductor device. The plug members are inserted into the receptacle member to interconnect the first and second semiconductor devices. The plug members may be removed from the receptacle member to disconnect the first and second semiconductor devices.


Find Patent Forward Citations

Gurtler, Richard. (1995). Method of shaping inter-substrate plug and receptacles interconnects (U.S. Patent No. 5457879). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5457879

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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