The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 1995

Filed:

Dec. 23, 1992
Applicant:
Inventor:

Gopi Ganapathy, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
371 24 ; 371 223 ; 371 251 ; 371 27 ; 364490 ;
Abstract

A test circuit and test technique for scan testing integrated circuits includes scan cells or capture scan elements arranged in a pseudo master slave configuration. The testing technique utilizes a first independent scan cell as a master stage and a second independent scan cell as a slave stage for propagating data through the IC. The test circuit and test techniques are highly advantageous because of minimal structural overhead. However, the scan cells must be loaded twice to recover the test data because half of the test data is lost when the data is propagated through the IC. The shift register inputs of one scan cell are generally coupled to shift register outputs of other scan cells. Each scan cell generally only includes one latch element.


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