Circuitry and method for programming and erasing a non-volatile

Abstract

Erase control circuitry for erasing a flash memory array. The erase control circuitry resides on the same substrate as the flash memory array, along with a command state machine. The command state machine recognizes and externally generated erase command applied to the terminals and generates an active erase control signal, to which the erase control circuitry responds. The erase control circuitry includes precondition pulse application circuitry, erase pulse application circuitry and erase verification circuitry. The precondition pulse application circuitry preconditions the array by programming each bit in the flash memory to a threshold voltage level representative of a programmed state. The erase pulse application circuitry applies a single erase pulse at a time to the flash memory array to erase the flash array by bringing the threshold voltage level of each cell in the array to a level representative of an erased state. The erase verification circuitry verifies the erasure of the flash memory array on a byte by byte basis. If the byte currently being verified has been erased; the erase verification circuitry brings a match signal to an active level. The erase control circuitry determines whether additional erase pulses should be applied to the flash array based upon the match signal and the number of erase pulses previously applied to the flash array described is program control circuitry and methods of programming and erasing a flash memory array in response to two step command sequences.