Apparatus for performing logic simulation

Abstract

A logic simulation apparatus which performs logic simulation of an operation of a logic circuit which includes at least a plurality of logic cells and a plurality of nets connecting the logic cells together, including a check circuit having at least one data input to which a data input signal is applied, a clock input to which a clock signal is applied, and an output. The check circuit compares the data input signal with a predetermined data value at a timing determined by the clock input signal and produces at its output a timing error detection signal based on the comparison. A memory cell is connected to the check circuit and has the data input signal applied to one input thereof, and the output signal of the check circuit applied to another input of said memory cell. The memory cell outputs the data input signal when the timing error detection circuit indicates that no timing error has occurred and outputs a signal which exhibits neither a high level nor a low level when the timing error detection signal indicates a timing error has occurred. Thereafter, logic simulation is executed on the basis of the output signal output by the memory cell so that said output signal is immediately propagated in the logic simulation.