Method and apparatus for cycle tracking variable delay lines

Abstract

Peripheral components are interfaced to a computer system through cycle tracking variable delay lines. The computer system includes a system I/O containing, in part, a bus cycle tracking apparatus. The bus cycle tracking apparatus includes cycle tracking logic, a plurality of delay lines, leading and trailing multiplexors (MUXs) and a state MUX. The bus cycle tracking apparatus controls the asynchronous delay of an output reference signal. A plurality of leading and trailing timing reference signals are provided as inputs to the plurality of delay lines. The leading and trailing timing references are delayed by the delay lines a time specified in accordance with an AC timing specification. The bus cycle is tracked such that during a leading/idle state, the leading timing reference is selected as the output reference, and during a trailing state, the trailing reference is selected. The independent control of the output reference signal allows all bus cycle events to be controlled precisely and independently.