Non-rectangular mos device configurations for gate array type integrated

Abstract

A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses. The busses are formed on the gate array structure over field oxide portions thereof during an initial step of patterning the layer of conductive material to expose active areas of differing conductivity type and to form the electrodes thereover. After further processing to form other electrode regions in the active areas such as source and drain regions, but prior to formation of an insulation layer over the structure for formation of a metal layer thereon, the busses are subjected to a further patterning step to form custom interconnections between various electrodes in the gate array structure so as to form a desired custom chip.