Method for the fabrication of dynamic random access memory capacitor

Abstract

A method for fabricating a dynamic random access memory capacitor. It is characterized by forming multi-insulating films with different etch selection ratio between conduction layers over a planarizing film, making the upper and lower portion of conduction pattern undercut by use of the difference in etch selection ratio when defining the capacitor into a pin structure, forming the insulating spacer in such a way to fill the undercut portions, forming the conduction spacer at the side wall of the insulating spacer, and etching the conduction layer at the inside of the insulating spacer, in a predetermined thickness, to form the inside conduction spacer. Accordingly, the capacitor fabricated by the method is structured to have a plurality of pin-shaped conduction layers with each being coated with a conduction spacer. Since the method takes advantage of the difference in etch selection ratio, it employs few etch masks, which facilitates the fabrication of DRAM capacitor. In addition, the increase of surface area by the conduction spacers results in the increase of capacitance in the capacitor. Furthermore, the capacitor has fewer steps than the conventional ones with the same capacitance, so that the method has significant advantage over conventional methods, including the capability of coating the steps.